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general description the max1124 is a monolithic 10-bit, 250msps analog-to-digital converter (adc) optimized for outstanding dynamic performance at high if frequencies up to 500mhz. the product operates with conversion rates of up to 250msps while consuming only 477mw. at 250msps and an input frequency of 100mhz, the max1124 achieves a spurious-free dynamic range (sfdr) of 71dbc. its excellent signal-to-noise ratio (snr) of 57.1db at 10mhz remains flat (within 1db) for input tones up to 500mhz. this makes the max1124 ideal for wideband applications such as digital predis- tortion in cellular base-station transceiver systems. the max1124 requires a single 1.8v supply. the ana- log input is designed for either differential or single- ended operation and can be ac- or dc-coupled. the adc also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock fre- quencies as high as 500mhz. this helps to reduce the phase noise of the input clock source. a differential lvds sampling clock is recommended for best perfor- mance. the converter? digital outputs are lvds com- patible, and the data format can be selected to be either two? complement or offset binary. the max1124 is available in a 68-pin qfn with exposed pad (ep) and is specified over the industrial (-40? to +85?) temperature range. for pin-compatible, lower speed versions of the max1124, refer to the max1122 (170msps) and the max1123 (210msps) data sheets. for a pin-compatible 8-bit version of the max1124, refer to the max1121 data sheet. applications wireless and wired broadband communicationcable-head end systems digital predistortion receivers communications test equipment radar and satellite subsystems antenna array processing features ? 250msps conversion rate ? snr = 56.8db/55.5db at f in = 100mhz/500mhz ? sfdr = 71dbc/63.8dbc at f in = 100mhz/500mhz ? npr = 54.8db at f notch = 28.8mhz ? single 1.8v supply ? 477mw power dissipation at 250msps ? on-chip track-and-hold and internal reference ? on-chip selectable divide-by-2 clock input ? lvds digital outputs with data clock output ? evaluation kit available (order max1124evkit) max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications ________________________________________________________________ maxim integrated products 1 5859606162 54555657 63 38 39 40 41 42 43 44 45 46 47 av cc agnd av cc top view av cc ogndov cc orporn d9p d9n d8p d8n 5253 d7p d7n agndagnd av cc clkn clkp av cc agnd ov cc ognd n.c. ov cc n.c. n.c.n.c. d4pd4n ognd ov cc dclkp dclknov cc d3p d3n d2p 35 36 37 d2n d1p d1n agnd inn inp agnd av cc agnd agnd av cc av cc av cc agnd refadj refio agnd 48 d5n av cc 64 agnd 656667 agndagnd av cc 68 t/b 2322212019 27262524 18 2928 323130 d0n d0p 3433 49 50 d6nd5p 51 d6p 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 clkdiv 17 max1124 ep pin configuration ordering information 19-3029; rev 2; 8/08 for pricing delivery, and ordering information please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max1124egk -40 c to +85 c 68 qfn-ep* * ep = exposed pad. downloaded from: http:///
max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc to agnd ......................................................-0.3v to +2.1v ov cc to ognd .....................................................-0.3v to +2.1v av cc to ov cc .......................................................-0.3v to +2.1v agnd to ognd ....................................................-0.3v to +0.3v analog inputs to agnd ...........................-0.3v to (av cc + 0.3v) digital inputs to agnd.............................-0.3v to (av cc + 0.3v) ref, refadj to agnd............................-0.3v to (av cc + 0.3v) digital outputs to ognd .........................-0.3v to (ov cc + 0.3v) esd on all pins (human body model).............................?000v continuous power dissipation (t a = +70?) 68-pin qfn (derate 41.7mw/? above +70?) .........3333mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? maximum current into any pin............................................50ma electrical characteristics(av cc = ov cc = 1.8v, v agnd = v ognd = 0, f sample = 250mhz, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ?%, c l = 5pf, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity inl (note 1) -2.4 0.8 +2.4 lsb differential nonlinearity dnl no missing codes (note 1) -1.0 0.5 +1.5 lsb t a +25? -25 +25 transfer curve offset v os (note 1) (note 2) -37 +37 lsb offset temperature drift ?0 ?/ c analog inputs (inp, inn) full-scale input voltage range v fs (note 1) 1100 1250 1375 mv p-p full-scale range temperaturedrift 130 ppm/ c common-mode input range v cm 1.38 ?.18 v input capacitance c in 3p f differential input resistance r in 3.00 4.3 6.25 k full-power analog bandwidth fpbw figure 8 600 mhz reference (refio, refadj) reference output voltage v refio 1.18 1.24 1.30 v reference temperature drift 90 ppm/ c refadj input high voltage v refadj used to disable the internal reference av cc - 0.3 v sampling characteristics maximum sampling rate f sample 250 mhz minimum sampling rate f sample 20 mhz downloaded from: http:///
max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications _______________________________________________________________________________________ 3 electrical characteristics (continued)(av cc = ov cc = 1.8v, v agnd = v ognd = 0, f sample = 250mhz, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ?%, c l = 5pf, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units clock duty cycle set by clock management circuit 40 to 60 % aperture delay t ad 350 ps aperture jitter t aj 0.2 ps rms clock inputs (clkp, clkn) differential clock input amplitude (note 2) 200 500 mv p-p clock input common-modevoltage range 1.15 0.25 v clock differential inputresistance r clk 11 25% k clock differential inputcapacitance c clk 5p f dynamic characteristics (at -0.5dbfs) f in = 10mhz, t a +25 c 54.3 57.1 f in = 100mhz, t a +25 c5 4 56.8 f in = 180mhz 56.3 signal-to-noise ratio snr f in = 500mhz 55.5 db f in = 10mhz, t a +25 c5 4 5 7 f in = 100mhz, t a +25 c 53.5 56.5 f in = 180mhz 56 signal-to-noiseand distortion sinad f in = 500mhz 55 db f in = 10mhz, t a +25 c 62.6 75 f in = 100mhz, t a +25 c6 2 7 1 f in = 180mhz 68.3 spurious-freedynamic range sfdr f in = 500mhz 63.8 dbc f in = 10mhz -75 f in = 100mhz -71 f in = 180mhz -68.3 worst harmonics(hd2 or hd3) f in = 500mhz -63.8 dbc imd 100 f in1 = 99mhz at -7dbfs, f in2 = 101mhz at -7dbfs -65 two-tone intermodulationdistortion imd 500 f in1 = 498.5mhz at -7dbfs, f in2 = 502.5mhz at -7dbfs -56 dbc lvds digital outputs (d0p/n?9p/n, orp/n) differential output voltage |v od | 250 450 mv downloaded from: http:///
max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications 4 _______________________________________________________________________________________ electrical characteristics (continued)(av cc = ov cc = 1.8v, v agnd = v ognd = 0, f sample = 250mhz, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ?%, c l = 5pf, t a = t min to t max , unless otherwise noted. +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units output offset voltage ov os 1.125 1.310 v lvcmos digital inputs (clkdiv, t /b) digital input voltage low v il 0.2 x av cc v digital input voltage high v ih 0.8 x av cc v timing characteristics clk to data propagation delay t pdl figure 4 1.5 ns clk to dclk propagation delay t cpdl figure 4 2.85 ns data valid to dclk rising edge t cpdl - t pdl figure 4 (note 2) 0.92 1.35 1.86 ns lvds output rise-time t rise 20% to 80%, c l = 5pf 460 ps lvds output fall-time t fall 20% to 80%, c l = 5pf 460 ps output data pipeline delay t latency 8 clock cycles power requirements analog supply voltage range av cc 1.7 1.8 1.9 v digital supply voltage range ov cc 1.7 1.8 1.9 v analog supply current i avcc f in = 100mhz 220 290 ma digital supply current i ovcc f in = 100mhz 45 75 ma total power dissipation p diss f in = 100mhz 477 657 mw offset 1.6 mv/v power-supply rejection ratio(note 3) psrr gain 1.9 %fs/v note 1: static linearity and offset parameters are computed from a best-fit straight line through the code transition points. the full-scale range is defined as 1023 x slope of the line. note 2: parameter guaranteed by design and characterization; t a = t min to t max . note 3: psrr is measured with both analog and digital supplies connected to the same potential. downloaded from: http:///
max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications _______________________________________________________________________________________ 5 -100 -80-90 -60-70 -40-50 -30 -10-20 0 fft plot (8192-point data record, coherent sampling) max1124 toc01 analog input frequency (mhz) amplitude (db) 04 0 6 0 8 0 20 100 140 120 f sample = 250.0057mhz f in = 11.5054mhz a in = -0.4795dbfs snr = 56.5dbsfdr = 73.5dbc hd2 = -82.4dbc hd3 = -73.5dbc hd2 hd3 -100 -80-90 -60-70 -40-50 -30 -10-20 0 fft plot (8192-point data record, coherent sampling) max1124 toc02 analog input frequency (mhz) amplitude (db) 04 0 6 0 8 0 20 100 140 120 f sample = 250.0057mhz f in = 60.0294mhz a in = -0.4885dbfs snr = 56.4dbsfdr = 74.6dbc hd2 = -82.1dbc hd3 = -75.6dbc hd2 hd3 -100 -80-90 -60-70 -40-50 -30 -10-20 0 04 0 6 0 8 0 20 100 140 120 fft plot (8192-point data record, coherent sampling) max1124 toc03 analog input frequency (mhz) amplitude (db) f sample = 250.0057mhz f in = 183.5064mhz a in = -0.5335dbfs snr = 56dbsfdr = 68.7dbc hd2 = -78.1dbc hd3 = -68.7dbc hd2 hd3 -100 -80-90 -60-70 -40-50 -30 -10-20 0 fft plot (8192-point data record, coherent sampling) max1124 toc04 analog input frequency (mhz) amplitude (db) 04 0 6 0 8 0 20 100 140 120 hd3 hd2 f sample = 250.0057mhz f in = 500.516mhz a in = -0.5155dbfs snr = 55.4dbsfdr = 64.8dbc hd2 = -69.9dbc hd3 = -64.8dbc fundamental snr vs. analog input frequency (f sample = 250.0057mhz, a in = -0.5dbfs) max1124 toc05 f in (mhz) snr (db) 400 300 200 100 51 52 5553 5754 56 5850 0 500 sfdr vs. analog input frequency (f sample = 250.0057mhz, a in = -0.5dbfs) max1124 toc06 f in (mhz) sfdr (dbc) 400 300 200 100 45 50 6555 6035 40 70 75 8030 0 500 hd2/hd3 vs. analog input frequency (f sample = 250.0057mhz, a in = -0.5dbfs) max1124 toc07 f in (mhz) hd2/hd3 (dbc) 400 300 200 100 -90 -80 -70 -60 -50 -100 0 500 hd2 hd3 27 3732 5247 42 57 62 -28 -16 -12 -24 -20 -8 -4 0 snr vs. analog input amplitude (f sample = 250.0057mhz, f in = 60.0294mhz) max1124 toc08 analog input amplitude (dbfs) snr (db) 40 6050 5545 7065 75 80 -28 -16 -12 -24 -20 -8 -4 0 sfdr vs. analog input amplitude (f sample = 250.0057mhz, f in = 60.0294mhz) max1124 toc09 analog input amplitude (dbfs) sfdr (dbc) typical operating characteristics (av cc = ov cc = 1.8v, v agnd = v ognd = 0, f sample = 250.0057mhz, -0.5dbfs; see tocs for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 , t a = +25?.) downloaded from: http:///
max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications 6 _______________________________________________________________________________________ -90 -75-80 -85 -60-65 -70 -50-55 -45 -40 -28 -16 -12 -24 -20 -8 -4 0 hd2/hd3 vs. analog input amplitude (f sample = 250.0057mhz, f in = 60.0294mhz) max1124 toc10 analog input amplitude (dbfs) hd2/hd3 (dbc) hd3 hd2 snr vs. f sample (f in = 60.0294mhz, a in = -0.5dbfs) max1124 toc11 f sample (mhz) snr (db) 50 5251 5453 5655 57 5850 10 250 170 130 90 210 sfdr vs. f sample (f in = 60.0294mhz, a in = -0.5dbfs) max1124 toc12 f sample (mhz) sfdr (dbc) 210 130 90 50 50 60 70 80 9040 10 250 170 hd2/hd3 vs. f sample (f in = 60.03294mhz, a in = -0.5dbfs) max1124 toc13 f sample (mhz) hd2/hd3 (dbc) 210 170 130 90 50 -95 -85 -75 -65-90 -80 -70 -60 -100 10 250 hd2 hd3 -100 -80-90 -60-70 -40-50 -30 -10-20 0 two-tone imd plot (8192-point data record, coherent sampling) max1124 toc14 analog input frequency (mhz) amplitude (db) 04 0 6 0 8 0 20 100 140 120 f sample = 250.0057mhz f in1 = 99.0317mhz f in2 = 101.0459mhz a in1 = a in2 = -7dbfs imd = -65dbc 2f in1 - f in2 2f in2 - f in1 f in1 f in2 -1.0 -0.6-0.8 -0.2-0.4 0.2 0 0.4 0.80.6 1.0 256 384 128 0 512 640 768 896 1024 integral nonlinearity vs. digital output code max1124 toc15 digital output code inl (lsb) -0.6 -0.4 -0.2 0 0.40.2 0.6 256 384 128 0 512 640 768 896 1024 differential nonlinearity vs. digital output code max1124 toc16 digital output code dnl (lsb) 20 -2-4 -6 -8 -10-12 10 100 1000 gain bandwidth plot (f sample = 250.0057mhz, a in = -0.5dbfs) max1124 toc17 analog input frequency (mhz) gain (db) snr vs. temperature (f in = 65.0344mhz, f sample = 250.0057mhz, a in = -0.5dbfs) max1124 toc18 temperature ( c) snr (db) 60 35 10 -15 5251 5453 5655 5857 6059 50 -40 85 typical operating characteristics (continued) (av cc = ov cc = 1.8v, v agnd = v ognd = 0, f sample = 250.0057mhz, -0.5dbfs; see tocs for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 , t a = +25?.) downloaded from: http:///
max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications _______________________________________________________________________________________ 7 sinad vs. temperature (f in = 65.0344mhz, f sample = 250.0057mhz, a in = -0.5dbfs) max1124 toc19 temperature ( c) sinad (db) 60 35 10 -15 6059 58 57 56 55 54 53 52 51 50 -40 85 sfdr vs. temperature (f in = 65.0344mhz, f sample = 250.0057mhz, a in = -0.5dbfs) max1124 toc20 temperature ( c) sfdr (dbc) 60 35 10 -15 55 60 65 70 75 8050 -40 85 power dissipation vs. f sample (f in = 60.0294mhz, a in = -0.5dbfs) max1124 toc21 f sample (mhz) p diss (mw) 170 130 90 50 445435 465455 485475 495 505425 10 250 210 fs voltage vs. fs adjust resistor max1124 toc22 fs adjust resistor ( ) v fs (v) 900 800 600 700 200 300 400 500 100 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.341.16 0 1000 resistor value appliedbetween refadj and agnd resistor value appliedbetween refadj and refio figure 6 snr vs. voltage supply (f in = 60.0294mhz, a in = -0.5dbfs) max1124 toc23 voltage supply (v) snr (db) 2.0 1.9 1.8 1.7 1.6 6059 58 57 56 55 54 53 52 51 50 1.5 2.1 av cc = ov cc internal reference vs. supply voltage (f sample = 250.0057mhz) max1124 toc24 supply voltage (v) v refio (v) 2.0 1.9 1.8 1.7 1.6 1.2310 1.2320 1.2330 1.2340 1.23501.2300 1.5 2.1 measured at the refio pinrefadj = av cc = ov cc 0.0e+00 1.0e+04 3.0e+042.0e+04 4.0e+04 5.0e+04 6.0e+04 7.0e+04 8.0e+04 507 295 508 509 510 511 43 noise histogram (dc input, 128k-point data record) max1124 toc25 digital output noise code counts f sample = 250mhz 56333 74401 propagation delay times vs. temperature max1124 toc26 temperature ( c) propagation delay (ns) 60 35 10 -15 1 2 3 4 5 60 -40 85 t cpdl t pdl typical operating characteristics (continued) (av cc = ov cc = 1.8v, v agnd = v ognd = 0, f sample = 250.0057mhz, -0.5dbfs; see tocs for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 , t a = +25?.) downloaded from: http:///
max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications 8 _______________________________________________________________________________________ pin description pin name function 1, 6, 11?4, 20, 25, 62, 63, 65 av cc analog supply voltage. bypass each pin with a 0.1? capacitor for best decoupling results. 2, 5, 7, 10, 15, 16,18, 19, 21, 24, 64, 66, 67, ep agnd analog converter ground. connect the converter? exposed pad (ep) to agnd. 3 refio reference input/output. with refadj pulled high through a 1k resistor, this i/o port allows an external reference source to be connected to the max1124. with refadj pulled lowthrough the same 1k resistor, the internal 1.23v bandgap reference is active. 4 refadj reference-adjust input. refadj allows for full-scale range adjustments by placing a resistoror trim potentiometer between refadj and agnd (decreases fs range) or refadj and refio (increases fs range). if refadj is connected to av cc through a 1k resistor, the internal reference can be overdriven with an external source connected to refio. if refadjis connected to agnd through a 1k resistor, the internal reference is used to determine the full-scale range of the data converter. 8 inp positive analog input terminal 9 inn negative analog input terminal 17 clkdiv clock divider input. this lvcmos-compatible input controls which speed the converter? digital outputs are updated. clkdiv has an internal pulldown resistor. clkdiv = 0: adc updates digital outputs at one-half the input clock rate. clkdiv = 1: adc updates digital outputs at the input clock rate. 22 clkp true clock input. this input requires an lvds-compatible input level to maintain theconverter? excellent performance. 23 clkn complementary clock input. this input requires an lvds-compatible input level to maintainthe converter? excellent performance. 50 5857 5955 54 5652 51 53 60 30 48 54 36 42 60 66 72 sinad vs. clock duty cycle (f in = 1.8148mhz, f sample = 249.856mhz, a in = -0.5dbfs) max1124 toc27 clock duty cycle (%) sinad (db) -100 -80-90 -60-70 -50 -40 5 101520253035 noise power ratio plot max1124 toc28 analog input frequency (mhz) power spectral density (db) f sample = 250mhz f notch = 28.8mhz npr = 54.8db typical operating characteristics (continued) (av cc = ov cc = 1.8v, v agnd = v ognd = 0, f sample = 250.0057mhz, -0.5dbfs; see tocs for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 , t a = +25?.) downloaded from: http:///
max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications _______________________________________________________________________________________ 9 pin description (continued) pin name function 26, 45, 61 ognd digital converter ground. ground connection for digital circuitry and output drivers. 27, 28, 41, 44, 60 ov cc digital supply voltage. bypass with a 0.1? capacitor for best decoupling results. 29?2 n.c. no connection. do not connect to these pins. 33 d0n complementary output bit 0 (lsb) 34 d0p true output bit 0 (lsb) 35 d1n complementary output bit 1 36 d1p true output bit 1 37 d2n complementary output bit 2 38 d2p true output bit 2 39 d3n complementary output bit 3 40 d3p true output bit 3 42 dclkn complementary clock output. this output provides an lvds-compatible output level and canbe used to synchronize external devices to the converter clock. there is a 2.1ns delay between clkn and dclkn. 43 dclkp true clock output. this output provides an lvds-compatible output level and can be used tosynchronize external devices to the converter clock. there is a 2.1ns delay between clkp and dclkp. 46 d4n complementary output bit 4 47 d4p true output bit 4 48 d5n complementary output bit 5 49 d5p true output bit 5 50 d6n complementary output bit 6 51 d6p true output bit 6 52 d7n complementary output bit 7 53 d7p true output bit 7 54 d8n complementary output bit 8 55 d8p true output bit 8 56 d9n complementary output bit 9 (msb) 57 d9p true output bit 9 (msb) 58 orn complementary output for out-of-range control bit. if an out-of-range condition is detected,bit orn flags this condition by transitioning low. 59 orp true output for out-of-range control bit. if an out-of-range condition is detected, bit orpflags this condition by transitioning high. 68 t /b two? complement or binary output format selection. this lvcmos-compatible inputcontrols the digital output format of the max1124. t /b has an internal pulldown resistor. t /b = 0: two? complement output format t /b = 1: binary output format downloaded from: http:///
max1124 detailed description?heory of operation the max1124 uses a fully differential, pipelined archi-tecture that allows for high-speed conversion, opti- mized accuracy and linearity, while minimizing power consumption and die size. both positive (inp) and negative/complementary analog input terminals (inn) are centered around a common- mode voltage of 1.4v, and accept a differential analog input voltage swing of ?.3125v each, resulting in a typi- cal differential full-scale signal swing of 1.25v p-p . inp and inn are buffered prior to entering each track-and-hold (t/h) stage and are sampled when the differen- tial sampling clock signal transitions high. a 2-bit adc following the first t/h stage then digitizes the signal, and controls a 2-bit digital-to-analog converter (dac). digitized and reference signals are then subtracted,resulting in a fractional residue signal that is amplified before it is passed on to the next stage through another t/h amplifier. this process is repeated until the applied input signal has successfully passed through all stages of the 10-bit quantizer. finally, the digital outputs of all stages are combined and corrected for in the digital cor- rection logic to generate the final output code. the result is a 10-bit parallel digital output word in user-selectable two? complement or binary output formats with lvds- compatible output levels. see figure 1 for a more detailed view of the max1124 architecture. 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications 10 ______________________________________________________________________________________ clock- divider control clock management t/h 10-bit pipeline quantizer core reference lvds data port 10 common-mode buffer input buffer clkdiv clkp clkn inp inn refio refadj 2.2k 2.2k dclkpdclkn d0p/n?9p/n orp orn max1124 figure 1. max1124 block diagram av cc agnd inn inp to common-mode input 2.2k to common-mode input 2.2k figure 2. simplified analog input architecture reference buffer refio refadj av cc av cc /2 control line to disable reference buffer adc full-scale = reft - refb g 1v 1k 0.1 f reference scaling amplifier reft refb figure 3. simplified reference architecture downloaded from: http:///
analog inputs (inp, inn) inp and inn are the fully differential inputs of themax1124. differential inputs usually feature good rejec- tion of even-order harmonics, which allows for enhanced ac performance as the signals are progressing through the analog stages. the max1124 analog inputs are self- biased at a common-mode voltage of 1.4v and allow a differential input voltage swing of 1.25v p-p . both inputs are self-biased through 2.2k resistors, resulting in a typical differential input resistance of 4.4k . it is recom- mended to drive the analog inputs of the max1124 inac-coupled configuration to achieve best dynamic per- formance. see the ac-coupled analog inputs section for a detailed discussion of this configuration. on-chip reference circuit the max1124 features an internal 1.23v bandgap ref-erence circuit (figure 3), which, in combination with an internal reference-scaling amplifier, determines the full- scale range of the max1124. bypass refio with a 0.1? capacitor to agnd. to compensate for gain errors or increase the adc? full-scale range, the volt- age of this bandgap reference can be indirectly adjust- ed by adding an external resistor (e.g., 100k trim potentiometer) between refadj and agnd or refadjand refio. see the applications information section for a detailed description of this process. clock inputs (clkp, clkn) designed for a differential lvds clock input drive, it isrecommended to drive the clock inputs of the max1124 max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications ______________________________________________________________________________________ 11 inp inn d0p/n?9p/n orp/n clkp clkn t ch t cl dclkp dclkn n - 8 n - 7 n n + 1 t pdl n - 7 n - 8 n n + 1 n n + 1 n + 8 n + 9 t cpdl t latency t ad n - 1 sampling event sampling event sampling event sampling event t cpdl - t pdl t cpdl - t pdl ~ 0.4 x t sample with t sample = 1/f sample note: the adc samples on the rising edge of clkp. the rising edge of dclkp can be used to externally latch the output data. figure 4. system and output timing diagram ov cc ognd 2.2k 2.2k v op v on figure 5. simplified lvds output architecture downloaded from: http:///
max1124 with an lvds-compatible clock to achieve the bestdynamic performance. the clock signal source must be a high-quality, low phase noise to avoid any degrada- tion in the noise performance of the adc. the clock inputs (clkp, clkn) are internally biased to 1.2v, accept a differential signal swing of 0.2v p-p to 1.0v p-p and are usually driven in ac-coupled configuration.see the differential, ac-coupled clock input in the applications information section for more circuit details on how to drive clkp and clkn appropriately.although not recommended, the clock inputs also accept a single-ended input signal. the max1124 also features an internal clock manage- ment circuit (duty-cycle equalizer) that ensures that the clock signal applied to inputs clkp and clkn is processed to provide a 50% duty cycle clock signal, which desensitizes the performance of the converter to variations in the duty cycle of the input clock source. note that the clock duty-cycle equalizer cannot be turned off externally and requires a minimum clock fre- quency of >20mhz to work appropriately and accord- ing to data sheet specifications. clock outputs (dclkp, dclkn) the max1124 features a differential clock output, whichcan be used to latch the digital output data with an external latch or receiver. additionally, the clock output can be used to synchronize external devices (e.g.,fpgas) to the adc. dclkp and dclkn are differential outputs with lvds-compatible voltage levels. there is a 2.1ns delay time between the rising (falling) edge of clkp (clkn) and the rising edge of dclkp (dclkn). see figure 4 for timing details. divide-by-2 clock control (clkdiv) the max1124 offers a clock control line (clkdiv),which supports the reduction of clock jitter in a system. connect clkdiv to ognd to enable the adc? internal divide-by-2 clock divider. data is now updated at one- half the adc? input clock rate. clkdiv has an internal pulldown resistor and can be left open for applications that only operate with update rates one-half of the con- verter? sampling rate. connecting clkdiv to ov cc allows data to be updated at the speed of the adc inputclock. system timing requirements figure 4 depicts the relationship between the clockinput and output, analog input, sampling event, and data output. the max1124 samples on the rising (falling) edge of clkp (clkn). output data is valid on the next rising (falling) edge of the dclkp (dclkn) clock, but has an internal latency of nine clock cycles. 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications 12 ______________________________________________________________________________________ inp analog voltage level inn analog voltage level out-of-range orp (orn) binary digital output code (d9?0) two? complement digital output code (d9?0) > v cm + 0.3125v < v cm - 0.3125v 1 (0) 11 1111 1111 (exceeds positive full scale, or set) 01 1111 1111 (exceeds positive full scale, or set) v cm + 0.3125v v cm - 0.3125v 0 (1) 11 1111 1111 (represents positive full scale) 01 1111 1111 (represents positive full scale) v cm v cm 0 (1) 10 0000 0000 or 01 1111 1111 (represents midscale) 00 0000 0000 or 11 1111 1111 (represents midscale) v cm - 0.3125v v cm + 0.3125v 0 (1) 00 0000 0000 (represents negative full scale) 10 0000 0000 (represents negative full scale) < v cm - 0.3125v > v cm + 0.3125v 1 (0) 00 0000 0000 (exceeds negative full scale, or set) 10 0000 0000 (exceeds negative full scale, or set) table 1. max1124 digital output coding downloaded from: http:///
digital outputs (d0p/n?9p/n, dclkp/n, orp/n) and control input t /b the digital outputs d0p/n?9p/n, dclkp/n, andorp/n are lvds compatible, and data on d0p/n?9p/n is presented in either binary or two? complement format (table 1). the t /b control line is an lvcmos-compatible input, which allows the user toselect the desired output format. pulling t /b low outputs data in two? complement and pulling it high presentsdata in offset binary format on the 10-bit parallel bus. t /b has an internal pulldown resistor and may be left unconnected in applications using only two? comple-ment output format. all lvds outputs provide a typical voltage swing of 0.4v around a common-mode voltage of approximately 1.2v, and must be terminated at the far end of each transmission line pair (true and comple- mentary) with 100 . the lvds outputs are powered from a separate power supply, which can be operatedbetween 1.7v and 1.9v. the max1124 offers an additional differential output pair (orp, orn) to flag out-of-range conditions, where out of range is above positive or below negative full scale. an out-of-range condition is identified with orp (orn) transitioning high (low). note: although differential lvds reduces single-ended transients to the supply and ground planes, capacitiveloading on the digital outputs should still be kept as low as possible. using lvds buffers on the digital outputs of the adc when driving off-board may improve overall performance and reduce system timing constraints. applications information full-scale range adjustments using the internal bandgap reference the max1124 supports a full-scale adjustment range of10% (?%). to decrease the full-scale range, an exter- nal resistor value ranging from 13k to 1m may be added between refadj and agnd. a similarapproach can be taken to increase the adcs full-scale range. adding a variable resistor, potentiometer, or pre- max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications ______________________________________________________________________________________ 13 reference buffer refio refadj av cc av cc /2 control line to disable reference buffer adc full-scale = reft - refb g 1v 0.1 f reference- scaling amplifier reft refb 13k to 1m 13k to 1m figure 6. circuit suggestions to adjust the adc? full-scale range max1124 50 clkp clkn single-ended input terminal mc100lvel16 510 510 150 150 v clk vgnd 23 45 6 7 8 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f 10 d0p/n?9p/n av cc ov cc agnd ognd inp inn figure 7. differential, ac-coupled, pecl-compatible clock input configuration downloaded from: http:///
max1124 determined resistor value between refadj and refioincreases the full-scale range of the data converter. figure 6 shows the two possible configurations and their impact on the overall full-scale range adjustment of the max1124. do not use resistor values of less than 13k to avoid instability of the internal gain regulation loop for the bandgap reference. differential, ac-coupled, pecl-compatible clock input the preferred method of clocking the max1124 is differ-entially with lvds- or pecl-compatible input levels. to accomplish this, a 50 reverse-terminated clock signal source with low phase noise is ac-coupled into a fastdifferential receiver such as the mc100lvel16 (figure 7). the receiver produces the necessary pecl output levels to drive the clock inputs of the data converter. differential, ac-coupled analog input an rf transformer provides an excellent solution toconvert a single-ended source signal to a fully differen- tial signal, required by the max1124 for optimum dynamic performance. in general, the max1124 pro- vides the best sfdr and thd with fully differential input signals and it is not recommended to drive the adc inputs in single-ended configuration. in differential input mode, even-order harmonics are usually lower since inp and inn are balanced, and each of the adc inputs only requires half the signal swing compared to a sin- gle-ended configuration. figure 8 depicts a secondary-side termination of the 1:1 transformer into two separate 25 loads. terminating the transformer in this fashion reduces the potentialeffects of transformer parasitics. the source impedance combined with the shunt capacitance provided by a pcb and the adc? p arasitic capacitance reduce the combined bandwidth to approximately 550mhz. single-ended, ac-coupled analog input although not recommended, the max1124 can be usedin single-ended mode (figure 9). analog signals can be ac-coupled to the positive input inp through a 0.1? capacitor and terminated with a 50 resistor to agnd. the negative input should be 25 reverse-terminated and ac grounded with a 0.1? capacitor. grounding, bypassing, and board layout considerations the max1124 requires board layout design techniquessuitable for high-speed data converters. this adc pro- vides separate analog and digital power supplies. the analog and digital supply voltage pins accept input voltage ranges of 1.7v to 1.9v. although both supply types can be combined and supplied from one source, it is recommended to use separate sources to cut down on performance degradation caused by digital switch- ing currents, which can couple into the analog supply network. isolate analog and digital supplies (av cc and ov cc ) where they enter the pcb with separate networks 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications 14 ______________________________________________________________________________________ max1124 10 d0p/n?9p/n av cc ov cc agnd ognd inp inn 25 25 15 15 adt1?wt 0.1 f 0.1 f single-ended input terminal figure 8. transformer-coupled analog input configuration with secondary-side termination max1124 10 d0p/n?9p/n av cc ov cc agnd ognd 0.1 f single-ended input terminal 0.1 f inp inn 50 25 figure 9. single-ended ac-coupled analog input configuration downloaded from: http:///
of ferrite beads and capacitors to their correspondinggrounds (agnd, ognd). to achieve optimum performance, provide each supply with a separate network of a 47? tantalum capacitor in parallel with 10? and 1? ceramic capacitors. additionally, the adc requires each supply pin to be bypassed with separate 0.1? ceramic capacitors (figure 10). locate these capacitors directly at the adc supply pins or as close as possible to the max1124. choose surface-mount capacitors, which are preferably located on the same side as the converter, to save space and minimize the inductance. multilayer boards with separated ground and power planes produce the highest level of signal integrity. consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the adc? package. the two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. a major concern with this approach are the dynamic currents that may need to travel long dis- tances before they are recombined at a common source ground, resulting in large and undesirable ground loops. ground loops can add to digital noise by coupling back to the analog front end of the converter, resulting in increased spur activity and a decreased noise performance. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. to minimize the effects of digital noise coupling, ground return vias canbe positioned throughout the layout to divert digital switching currents away from the sensitive analog sec- tions of the adc. this does not require additional ground splitting, but can be accomplished by placing substantial ground connections between the analog front end and the digital outputs. the max1124 is packaged in a 68-pin qfn-ep pack- age (package code: g6800-4), providing greater design flexibility, increased thermal efficiency, and opti- mized ac performance of the adc. the ep must be soldered down to agnd.in this package, the data converter die is attached to an ep lead frame with the back of this frame exposed at the package bottom surface, facing the pcb side of the package. this allows a solid attachment of the package to the pcb with standard infrared (ir) flow soldering techniques. note that thermal efficiency is not the key factor, since the max1124 features low-power operation. the exposed pad is the key element to ensure a solid ground connection between the dac and the pcb? analog ground layer. considerable care must be taken, when routing the dig- ital output traces for a high-speed, high-resolution data converter. it is essential to keep trace lengths at a mini- mum and place minimal capacitive loading?ess than 5pf?n any digital trace to prevent coupling to sensi- tive analog sections of the adc. it is recommended to run the lvds output traces as differential lines with max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications ______________________________________________________________________________________ 15 max1124 10 d0p/n?9p/n av cc ov cc agnd ognd ognd agnd analog power- supply source digital/output- driver power- supply source bypassing?dc level bypassing?oard level note: each power-supply pin (analog and digital) should be decoupled with an individual 0.1 f capacitor close to the adc. 1 f1 0 f4 7 f av cc 0.1 f0 . 1 f 1 f1 0 f4 7 f ov cc figure 10. grounding, bypassing, and decoupling recommendations for the max1124 downloaded from: http:///
max1124 100 characteristic impedance from the adc to the lvds load device. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on anactual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. however, the static linearity parameters for the max1124 are mea- sured using the histogram method with an input fre- quency of 10mhz. differential nonlinearly (dnl) differential nonlinearity is the difference between anactual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. the max1124? dnl specification is measured with the his- togram method based on a 10mhz input tone. dynamic parameter definitions aperture jitter figure 11 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the falling edge of the sampling clock and the instant whenan actual sample is taken (figure 11). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digitalsamples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr db[max] = 6.02 db x n + 1.76 db in reality, other noise sources such as thermal noise,clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the snr calcula- tion and should be considered when determining the snr in adc. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig-nal to all spectral components excluding the fundamen- tal and the dc offset. in case of the max1124, sinad is computed from a curve fit. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre-quency (maximum signal component) to the rms value of the next-largest noise or harmonic distortion compo- nent. sfdr is usually measured in dbc with respect to the carrier frequency amplitude or in dbfs with respect to the adc? full-scale range. two-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels ofeither input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -7db full scale. 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications 16 ______________________________________________________________________________________ hold analog input sampled data (t/h) t/h t ad t aj track track clkn clkp figure 11. aperture jitter/delay specifications part resolution (bits) speed grade (msps) max1122 10 170 max1123 10 210 max1121 8 250 pin-compatible higher speed/ lower resolution versions package information for the latest package outline information and land patterns, goto www.maxim-ic.com/packages . package type package code document no. 68 qfn-ep g6800-4 21-0122 downloaded from: http:///
max1124 1.8v, 10-bit, 250msps analog-to-digital converter with lvds outputs for wideband applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision number revision date description pages changed 0 10/03 initial release 12 / 0 4 28 / 0 8 minor corrections to the data sheet to fix problems found during off-shore transfer. 3, 4 revision history downloaded from: http:///

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